The present invention relates to a digital-to-analog converter (DAC).
Digital-to-analog converters (DAC) are well known circuits used to convert digital signals to analog signals. One example of a conventional DAC is a current summing DAC, such as that described in Japanese Laid-Open Patent Publication No. 9-191252. The DAC shown in FIG. 1 of the publication has a 7-bit structure and is divided into a first DAC unit 11, which includes control transistors Q1, Q2, and Q3 for the lower three bits, and a second DAC unit 12, which includes control transistors Q4, Q5, Q6, and Q7 for the higher four bits. The DAC also includes a first drive transistor Q11, which forms a current mirror with each control transistor of the first DAC unit 11, and a second drive transistor Q12, which forms a current mirror with each control transistor of the second DAC unit 12. The first and second drive transistors Q11 and Q12 are respectively connected to first and second current sources Q21 and Q22, which form a current mirror with each other and supply each other with currents having different current values.
With this structure, the size of the control transistors located at the higher bit side (second DAC unit 12) and the size of the control transistors located at the lower bit side (first DAC unit 11) are independently adjusted based on the current ratio of the first and second current sources Q21 and Q22. This allows for reduction in the size of the control transistor Q7 for the highest bit that occupies the largest area in the layout of the transistors. However, this structure has a shortcoming in that a glitch is produced in the output voltage of the DAC when a digital code changes. That is, a glitch is produced when the gate-source voltage of each of the first and second drive transistors Q11 and Q12 fluctuates due to charging and discharging at the gate of the first drive transistor Q11 and the gate of the second drive transistor Q12. This is because changes in the gate-source voltage of each of the first and second drive transistors Q11 and Q12 change the values of currents I11 and I12, which flow to the transistors Q11 and Q12.
Another example of a DAC is a master-slave DAC, such as described in Japanese Laid-Open Patent Publication No. 2002-9623. FIG. 1 of the publication shows a DAC including a master circuit at a higher bit side and a slave circuit at a lower bit side. The master and slave circuits each employ an R-2R ladder, weighted current distribution structure. However, high operational power is required to drive each current mirror of the master circuit and slave circuit and obtain an output voltage with high linearity.
Japanese Laid-Open Patent Publication No. 2007-336540 describes a DAC structure that generates an analog signal by adding the currents distributed by a current distributor in accordance with a digital code. In such structure, however, the current distribution unit is formed by a plurality of cascode circuits to obtain a large current distribution ratio. Thus, in the same manner as Japanese Laid-Open Patent Publication No. 2002-9623, high operational power is necessary.